A thin film transistor integrated circuit device constitutes a microprocessor, a system LSI (large scale integration) circuit, or the like by disposing, on an insulator substrate such as a glass substrate or on a substrate of which at least the surface is an insulator, many thin film transistors and a single wiring layer or multiple wiring layers adapted to connect those transistors to each other and to a power supply and input/output terminals. As one of its embodiments, there is an active matrix display device such as an active matrix liquid crystal display device or an organic EL (electroluminescence) display device. The active matrix display device basically has pixels arranged in a matrix, thin film transistors (hereinafter abbreviated as TFTs) arranged in a matrix so as to correspond to the respective pixels and used as switching elements, and lines in a row direction and lines in a column direction forming a matrix. The lines in the row direction are used as scanning lines adapted to apply scan signals, transmitting signal write timings, to gate electrodes of the TFTs, while, the lines in the column direction are used as signal lines adapted to supply signals corresponding to a display image to the pixels through the TFT switches. Therefore, the signal lines are connected to ones of source electrodes and drain electrodes of the TFTs and the others of the source electrodes and the drain electrodes of the TFTs are connected to pixel electrodes. The TFT switch is turned on by a timing signal applied to the gate electrode from the scanning line, thereby supplying a signal to the pixel. Such active matrix display devices are classified into an active matrix liquid crystal display device, an organic EL display device, and so on according to kinds of pixels. The entire substrate including the scanning lines, the signal lines, and the TFTs is also called an active matrix substrate, which is constituted by forming, on the surface of the substrate, circuit patterns in layers through film formation processes, photolithography processes, and so on in a decompressed atmosphere. In terms of cost reduction of the display device, reduction of the film formation processes and the photolithography processes in the decompressed atmosphere has been discussed.
Particularly, the process of forming the wiring by sputtering is a main cause for increasing the manufacturing cost of the active matrix substrate because, since a wiring material formed over the entire surface is processed by a photolithography method to thereby form wiring portions, most of the material is removed by etching and, further, a material target, which is large as compared with the area of the substrate, is used for ensuring uniformity of the film thickness, and therefore, the material utilization efficiency is extremely low.
For solving such a problem, there has been developed a technique that forms wiring only at necessary portions by a printing method, thereby enhancing the material utilization efficiency. For example, Japanese Unexamined Patent Application Publication (JP-A) No. 2002-026014 (Patent Document 1) discloses a method of forming wiring at predetermined portions by the use of an inkjet method. By the use of such a printing method, the decompression process can be eliminated to reduce the manufacturing cost of the display device.
On the other hand, in active matrix display devices, there have been widely used TFT elements, operating as switching elements, of the inverted stagger type where gate electrodes are formed on the substrate side. The display device using the inverted stagger type TFTs is formed as described in Japanese Unexamined Patent Application Publication (JP-A) No. 2002-98994 (Patent Document 2) or the like. That is, in Patent Document 2, at first, gate electrodes are formed on a glass substrate by a photolithography method and, thereafter, a process of forming a gate insulating film is carried out. Then, an amorphous silicon layer and an n+-type amorphous silicon layer to be a contact layer are stacked as semiconductor layers. Separation between source and drain electrodes and the n+-type amorphous silicon layer forming contacts is carried out by the use of a halftone exposure technique that modulates the exposure amount by the use of a slit mask or the like so as to adjust the thickness of a resist after development and then performs etching. Subsequently, the remaining photoresist is stripped and passivation film formation at channel portions is carried out by a CVD (chemical vapor deposition) method.
Patent Document 1:
Japanese Unexamined Patent Application Publication No. 2002-026014
Patent Document 2:
Japanese Unexamined Patent Application Publication No. 2002-98994
Patent Document 3:
Specification of Japanese Patent Application No. 2003-159315
Patent Document 4:
Japanese Unexamined Patent Application Publication No. 2002-324966